A new transceiver invented by electrical engineers at the University of California, Irvine boosts radio frequencies into 140-gigahertz territory, unlocking data speeds that rival those of physical fiber-optic cables and laying the groundwork for a transition to 6G and FutureG data transmission protocols.
To create the transceiver, researchers in UC Irvine’s Samueli School of Engineering devised a unique architecture that blends digital and analog processing. The result is a silicon chip system, comprising both a transmitter and a receiver, that’s capable of processing digital signals significantly faster and with much greater energy efficiency than previously available technologies.
The team from UC Irvine’s Nanoscale Communication Integrated Circuits Labs outline its work in two papers published this month in the IEEE Journal of Solid-State Circuits. In one, the engineers discuss the technology they call a “bits-to-antenna” transmitter, and in the second, they cover their “antenna-to-bits” receiver.
Payam Heydari, UC Irvine Chancellor’s Professor of electrical engineering and computer science
“We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables,” said Payam Heydari, NCIC Labs director, UC Irvine Chancellor’s Professor of electrical engineering and computer science, and senior author of both papers. “By operating in the F-band – a frequency range well above current 5G standards — we can offer massive bandwidths that will transform how machines, robots and data centers communicate.”
He said the breakthrough is the culmination of a long-term strategic vision. His team began formulating the bits-to-antenna concept in 2020 after recognizing that traditional mixed-signal chip architectures that rely heavily on energy-gobbling data converters would “hit a performance wall” eventually.
“We realized that to reach the elusive 100-gigabit-per-second milestone — which is 100 times the speed of current wireless devices – without melting the chip, we had to fundamentally rethink the circuit topology,” Heydari said. “We envisioned novel, all-analog architectures that could overcome the severe power trade-offs plaguing high-speed designs.”
Team members understood that as speeds rose, the boundary between digital and analog had to shift. By moving the heavy lifting into the analog domain, they could bypass the inefficiencies that limit standard 5G chips. Heydari said that academic researchers and communications engineers have long faced a bottleneck: As wireless speeds increase, the power required to process that data usually skyrockets.
“If we stuck to traditional methods, the battery life of next-generation devices would vanish in minutes,” he said. “Our group’s answer is a transceiver that leapfrogs over current limitations by performing complex calculations in the analog domain, rather than the power-hungry digital domain.”
The new end-to-end transceiver operates at 120 gigabits per second, which is fast enough to transfer multiple 4K movies in the blink of an eye.
“The Federal Communications Commission and 6G standards bodies are looking at the 100-gigahertz spectrum as the new frontier,” said Zisong Wang, a former UC Irvine doctoral researcher in electrical engineering and computer science now working at Marvell Technology Inc. who’s lead author of the bits-to-antenna paper. “But at such speeds, conventional transmitters that create signals using digital-to-analog converters are incredibly complex and power-hungry and face what we call a DAC bottleneck.”
He said the team’s new transmitter eliminates the DAC entirely by constructing signals directly in the radio-frequency domain using three “It’s like packing a suitcase perfectly before leaving the house rather than trying to organize it while running to the airport,” Wang said.
Mohammad Oveisi, a UC Irvine doctoral student and a co-author of the antenna-to-bits article, explained that this method, known as RF-domain 64QAM, allows the chip to be incredibly efficient, sending more data without overheating the device. Having transmitters and receivers that can handle such high-frequency data is going to be vital in ushering in a new era dominated by internet-connected products, autonomous vehicles and AI edge computing, which allows artificial intelligence and machine learning applications to be run on local devices.
While this digital dream has driven technology developers for decades, stumbling blocks appeared, according to the lead author of the antenna-to-bits paper, Youssef Hassan, a former UC Irvine doctoral researcher in electrical engineering and computer science currently with Qualcomm.
“Traditional receivers struggle to catch such fast data without using massive, energy-draining components called analog-to-digital converters,” he said. “Moore’s law suggests we can just make transistors smaller to go faster, but at these extreme speeds, we hit a physical wall known as the sampling bottleneck. Digitizing a 120-Gbps signal typically requires massive analog-to-digital converters that burn watts of power, far too much for a smartphone.”
Instead of trying to force the electronics to work harder, the team designed a receiver that works smarter.
“We developed a technique called hierarchical analog demodulation,” Hassan explained. “By breaking the signal down hierarchically in the analog domain, peeling apart the complex data layers before they’re digitized, we extract the data using a fraction of the power typically required.”
He noted that the receiver chip, fabricated in 22-nanometer, fully depleted silicon-on-insulator technology, consumes only 230 milliwatts of power, making it efficient enough for portable devices.
Heydari said that in addition to enabling transmission in the 140-gigahertz range, the transceiver’s bits-to-antenna architecture allows it to be mass-produced at a lower cost, paving the way for widespread adoption.
“Our innovation eliminates the need for miles of complex copper wiring inside data centers,” he said. “Data farm operators can do ultrafast wireless links between server racks, saving considerable money on hardware, cooling and power.”
Heydari added that routine semiconductor fabrication services were utilized to support this research project, proving that these high-performance chips can be built using standard manufacturing processes.
The research was funded through the U.S. Department of Defense Microelectronics Commons program.
